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fully accurate 16-bit v out nano dac ? spi interface 2.7 v to 5.5 v, in an sot-23 ad5061 fea t ures single 16-bit d a c, 4 lsb inl p o w e r- on reset to midsc a le or z e ro -sc a le guar ant e ed m o not o ni c b y design 3 pow e r- down func tions l o w po w e r serial in t e r f ac e wit h s c hmitt-trigger e d inputs small 8 - lea d s o t - 23 pack age , low po w e r f a st settl ing ti me of 4 s t y pi c a lly 2.7 v t o 5. 5 v p o w e r sup p ly l o w glit ch on pow e r-up sy nc in t e rrupt facili t y applic a t io ns p r oc ess c o n t r o l da ta ac q u isitio n sy st ems p o r t able ba tt er y - pow e r e d instrumen t s digital gain an d off s et adjustmen t p r ogr a mmable v o ltage and curr ent sour c e s pro g r a m m a b l e at te n u ato r s func ti on a l bl ock di a g r a m a d 5061 v dd v ou t v re f po w e r - o n r eset dac r e g i st er dac in p u t co nt ro l logic po w e r - d o w n co n t ro l l o g i c res i s t o r ne t w o r k re f ( + ) scl k di n 04762- 001 syn c dacg nd buf a gn d ou tp u t b u ffe r figure 1. gener a l description the ad5061 , a m e m b er o f ad i s na no da c f a m i l y , i s a l o w p o w e r , sin g l e 16 -b i t b u f f er e d v o l t a g e-ou t d a c t h a t o p er a t es f r o m a sin g le 2. 7 v t o 5.5 v s u p p l y . the p a r t o f f e rs a r e l a ti v e acc u rac y sp e c if ica t ion o f 4 ls b a nd o p era t io n is gua r a n t e e d m o n o t o n i c w i t h a 1 ls b dnl sp e c if ic a t ion. t h e p a r t us es a v e rs a t i l e 3- w i r e s e r i al in t e r f ace t h a t o p er a t es a t clo c k ra t e s u p t o 30 mh z, and is co m p a t ib le wi th s t anda r d s p i?, qs p i ?, mi cro w ire? , a nd ds p in ter f ace st anda r d s. t h e r e fer e n c e fo r th e ad5061 is su p p lied f r o m a n ext e r n al v ref pi n . a re f e re nc e b u f f er is als o p r o v ided on-c hi p . the p a r t inco r p o r a t es a p o w e r - on re s e t c i rc u i t t h a t e n su re s t h e d a c output p o we r s up to m i d - s c ale o r zer o s c a l e a nd r e ma i n s t h er e u n t i l a vali d wr i t e t a k e s place t o t h e de v i ce . th e p a r t con t a i n s a p o w e r - do wn fe a t ur e tha t r e d u ces t h e c u r r en t co n s u m p t ion o f the device t o typ i cal l y 330 na a t 5 v and p r o v ides s o f t wa r e -s e l ec tab l e o u t p u t lo ads w h i l e in p o w e r - do wn m o de . t h e p a r t is p u t in to p o w e r - d o w n m o de o v er t h e s e r i al i n ter f ace . t o t a l unad j u s t e d er r o r fo r t h e p a r t is <3 mv . this p a r t exhi b i ts v e r y lo w g l i t c h o n p o w e r - u p . table 1. r e lated d e vices p a r t no . description ad5062 2.7 v to 5.5 v , 16 -bit nano d a c d/a , 1 lsb inl, so t - 2 3 ad5063 2.7 v to 5.5 v , 16 -bit nano d a c d/a , 1 lsb inl, msop ad5040/ad506 0 2.7 v to 5.5 v , 14 -bit/16-bit nano d a c d/a , 1 lsb inl, so t - 2 3 produc t highlight s 1. a v a i lab l e in a s m al l 8-le ad sot - 23 p a c k a g e . 2. 16-b i t acc u ra t e , 4 ls b inl. 3. lo w gli t c h o n p o w e r - u p . 4. h i gh s p eed s e ri a l i n t e rf a c e w i th c l o c k sp e e ds u p t o 3 0 m h z. 5. thr e e p o w e r - do w n m o des a v a i l a b l e t o t h e us er . 6. r e s e t to k n ow n output vo lt age ( m i d s c a l e or z e r o s c a l e ) . rev. a in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th ir d par t ies th a t m a y r e su l t f r o m i t s use . s p e c i f ica t io n s su bj e c t t o c h an g e w i th o u t n o ti c e . n o l i c e n s e i s g r an t e d b y imp l ic a t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g d e v i c e s . t r adem ar ks and r e g i st e r ed tr ad ema r ks ar e the p r o p er t y of the i r r e sp e c t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2006 a n alog de vices, i n c. al l r i ght s r e ser v ed .
ad5061 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 ter mi nolo g y .................................................................................... 14 theory of operation ...................................................................... 15 dac architecture ....................................................................... 15 reference buffer ......................................................................... 15 serial interface ............................................................................ 15 input shift register .................................................................... 15 sync interrupt .......................................................................... 15 power-on to zero-scale or midscale ...................................... 16 software reset ............................................................................. 16 power-down modes .................................................................. 16 microprocessor interfacing ....................................................... 16 applications ..................................................................................... 18 choosing a reference ................................................................ 18 bipolar operation ....................................................................... 18 using a galvanically-isolated interface chip ......................... 19 power supply bypassing and grounding ................................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 1/06rev. 0 to rev. a changes to general description .................................................... 1 changes to table 2............................................................................ 3 changes to figure 19 caption....................................................... 10 added figure 28 to figure 36........................................................ 12 changes to serial interface section.............................................. 15 changes to power-down modes section .................................... 16 changes to ordering guide .......................................................... 20 7/05revision 0: initial version
ad5061 rev. a | page 3 of 20 specifications v dd = 5.5 v, v ref = 4.096 v, r l = unloaded, c l = unloaded, t min to t max , unless otherwise specified. table 2. b grade 1 parameter min typ max unit test conditions/comments static performance resolution 16 bits relative accuracy (inl) 2 0.5 4 lsb ?40c to +85c, b grade 0.5 4 ?40c to +125c, y grade total unadjusted error (tue) 0.5 3.0 mv ?40c to +85c, b grade 0.5 3.0 ?40c to +125c, y grade differential nonlinearity (dnl) 0.5 1 lsb guaranteed monotonic, ?40c to +85c, b grade 0.5 1 guaranteed monotonic, ?40c to +125c, y grade gain error 0.01 0.05 % of fsr t a = ?40c to +85c, b grade 0.01 0.05 t a = ?40c to +125c , y grade gain error temperature coefficient 1 ppm of fsr/c offset error 0.02 3.0 mv t a = ?40c to + 85c, b grade 0.02 3.0 t a = ?40c to + 125c, y grade offset error temperature coefficient 0.5 v/c full-scale error 0.05 3.0 mv all 1s loaded to dac register, t a = ?40c to +85c, b grade 0.05 3.0 all 1s loaded to dac register, t a = ?40c to +125c , y grade output characteristics 3 output voltage range 0 v ref v output voltage settling time 4 s ? scale to ? scale code transition to 1lsb, r l = 5 k? output noise spectral density 64 nv/ hz dac code = midscale, 1 khz output voltage noise 6 v p-p dac code = midscale , 0.1 hz to 10 hz bandwidth digital-to-analog glitch impulse 2 nv-s 1 lsb change around major carry, r l = 5 k? digital feedthrough 0.003 nv-s dac code = full-scale dc output impedance (normal) 0.015 ? output impedance tolerance 10% dc output impedance (power-down) (output connected to 1 k? network) 1 k? output impedance tolerance 400 ? (output connected to 100 k? network) 100 k? output impedance tolerance 20 k? capacitive load stability 1 nf loads used: r l = 5 k?, r l = 100 k?, r l = output slew rate 1.2 v/s ? scale to ? scale code transition to 1 lsb, r l = 5 k?, c l = 200 pf short-circuit current 60 ma dac code = full-scale, output shorted to gnd, t a = 25c 45 ma dac code = zero-scale, output shorted to v dd , t a = 25c dac power-up time time to exit power-down mode to normal mode of ad5061, 24 th clock edge to 90% of dac final value, output unloaded dc power supply rejection ratio ?92 db v dd 10%, dac code = full-scale wideband spurious-free dynamic range ?67 db output frequency = 10 khz reference input/output v ref input range 4 2 v dd ? 50 mv input current (power-down) 0.1 a zero-scale loaded input current (normal) 0.5 a dc input impedance 1 m ?
ad5061 rev. a | page 4 of 20 b grade 1 parameter min typ max unit test conditions/comments logic inputs input current 5 1 5 a input low voltage (v il ) 0.8 v v dd = 4.5 v to 5.5 v 0.8 v dd = 2.7 v to 3.6 v input high voltage (v ih ) 2.0 v v dd = 2.7 v to 5.5 v 1.8 v dd = 2.7 v to 3.6 v pin capacitance 4 pf power requirements v dd 2.7 5.5 v all digital inputs at 0 v or v dd i dd (normal mode) dac active and excluding load current v dd = 2.7 v to 5.5 v 1.0 1.2 ma v in = v dd and v il = gnd, v dd = 5.5 v, v ref = 4.096 v, code = midscale 0.89 v in = v dd and v il = gnd, v dd = 3.0 v, v ref = 4.096 v, code = midscale i dd (all power-down modes) v dd = 2.5 v to 5.5 v 1 a v ih = v dd and v il = gnd, v dd = 5.5 v, v ref = 4.096 v, code = midscale 0.265 v ih = v dd and v il = gnd, v dd = 3.0 v, v ref = 4.096 v, code = midscale 1 temperature range for b grade: ?40c to +85c, typical at 25c; temperatur e range for y grade: ?40c to +125c. 2 linearity calculated using a re duced code range (160 to 65535). 3 guaranteed by design and characterization, not production tested. 4 the typical output supply headroom performance for various reference voltages at ?40c can be seen in . figure 27 5 total current flowing into all pins.
ad5061 r e v. a | pa ge 5 o f 2 0 timing characteristics v dd = 2.7 v t o 5.5 v , al l s p ec if ic a t io n s t min to t max , un less o t h e r w is e sp e c if ie d. table 3. p a r a me t e r l i m i t 1 u n i t t e st c o ndition s /c ommen t s t 1 2 33 ns min sclk c y cle time t 2 5 ns min sclk high time t 3 3 ns min sclk lo w time t 4 1 0 n s m i n sy nc t o sclk falling edge set - up time t 5 3 ns min da ta set-up time t 6 2 ns min da ta hold time t 7 0 n s m i n sclk falling edge t o sy nc ri s i n g e d g e t 8 1 2 n s m i n m i nimum sy nc high time t 9 9 n s m i n sy nc rising edge t o nex t sclk fall ig nor e 1 a l l i n put si gn a ls a r e sp eci f i e d wi t h t r = t f = 1 n s / v (10% t o 90% of v dd ) a n d t i m e d from a volt a g e lev e l o f (v il + v ih )/2. 2 ma xi m u m s c lk fre q uen c y i s 30 mh z. t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d22 d23 sy n c sc l k 047 62- 0 0 2 t 9 t 1 t 8 d23 d 22 di n figure 2. ti m i ng d i agra m
ad5061 r e v. a | pa ge 6 o f 2 0 absolute maximum ra tings table 4. p a r a me t e r r a t i n g v dd to gnd ?0.3 v to +7.0 v dig i tal i n put v o l t age to gnd ?0.3 v to v dd + 0.3 v v ou t to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v o p era t ing t e mp er a tur e r a nge i n dustr i al (b gr a d e) ?40c to + 85c ex t e nded a u t o motiv e t e mper atur e r a nge ( y gr ade) ?40c to +125c stor age t e mpera tur e r a nge ?65c to +150c m a ximum junc tion t e mpera tur e 150c so t - 23 p a ck age p o w e r di ssip a ti on ( t j max ? t a )/ ja ja ther mal i m pedanc e 206c/w jc ther mal i m pedanc e 44c/w r e flo w s o lder ing (pb - f r ee) p e ak t e mpera tur e 260c t ime -a t-p e ak t e mpera tur e 10 sec to 40 sec e s d 1 . 5 k v s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . this d e vice is a hig h p e r f o r ma nce in t e g r a t e d c i r c ui t wi t h an es d r a t i ng o f < 2 kv , and is esd-s e n s i t i v e. pr o p er p r e c a u t i on s sh o u l d b e t a ken fo r ha n d lin g and ass e m b ly . esd caution esd (elec t r o st a t ic dischar g e) se nsitiv e devic e . elec tr os t a tic char ges as high as 4000 v r e adily ac cumula te on the human bod y and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr oduc t f e a tur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t dama ge may oc cur on dev i c e s sub j ec ted to high ener gy elec tr o s ta tic di scharge s . theref or e , proper esd pr ecautio n s a r e r e c o m m ended to a v oid per f or man c e degrada t ion or l o ss of func tiona l it y .
ad5061 r e v. a | pa ge 7 o f 2 0 pin conf igura t ion and fu nction descriptions a d 5061 top vi e w ( n o t t o s cal e) v ou t sy n c 18 ag nd sc l k 27 di n da cg nd 36 04 76 2- 0 0 3 v re f 45 v dd figure 3. pin c o nfiguration ta ble 5. pi n f u nct i on d e s c ri pt i o ns p i n no . m n emonic description 1 d i n serial da ta i n put. t h is devic e has a 24-bit shif t r e g i st er . da ta is clocked in t o the r e g i st er on the falling edge of the ser i al cl ock in put. 2 v dd p o w e r sup p l y i n put. these par t s can be ope ra te d fr om 2.7 v to 5.5 v and v dd should be d e c o uple d to gnd . 3 v ref r e f e r e nc e v o lta g e i n put. 4 v ou t analog o utput v o ltage fr om d a c. 5 ag n d g r o u n d r e fe re n c e p o i n t fo r a n a l o g c i rc u i t r y . 6 d a c g nd gr ound i n put t o the d a c. 7 sy nc l e v e l- t r igger e d c o n t r o l i n put ( a c t iv e l o w). this is the fr ame synchr oniza t ion sig n al f o r the input da ta . w h en sy nc goes low , it ena b les the in put shif t r e gister and d a ta is transf er red in on the falli ng ed ges of the f o llowing cl ock s . the d a c is upd a ted f o llo wing th e 24th clock c y cl e unless sy nc is taken high bef o r e this edge , in whic h case the ri s i n g e d g e o f sy nc ac ts as an i n ter r upt and the wr it e sequenc e i s ign o r e d b y the d a c . 8 s c l k s e r i al clock i n p ut. da ta is clock e d in to the input shif t r e g i st er on the falling ed ge of the ser i al cl ock input. da ta can be transf er r e d at ra tes up to 30 mh z.
ad5061 r e v. a | pa ge 8 o f 2 0 typical perf orm ance cha r acte ristics 04 76 2- 00 4 16 0 ?1 . 6 ?1 . 4 ?1 . 2 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 60160 50160 40160 30160 20160 10160 i n l e rro r ( l s b ) d ac co d e t a = 2 5 c v dd = 5 v , v ref = 4 . 096v fig u re 4. ty pic a l in l pl ot 04 76 2- 00 5 16 0 ?0 . 1 6 ?0 . 1 4 ?0 . 1 2 ?0 . 1 0 ?0 . 0 8 ?0 . 0 6 ?0 . 0 4 ?0 . 0 2 0 0. 02 0. 04 0. 06 0. 08 0. 10 0. 12 0. 14 0. 16 60160 50160 40160 30160 20160 10160 t u e e r r o r ( m v) d ac co d e t a = 2 5 c v dd = 5 v , v ref = 4 . 096v fig u re 5. ty pic a l t u e plot 04 76 2- 00 6 160 ?1. 6 ?1. 4 ?1. 2 ?1. 0 ?0. 8 ?0. 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 60160 50160 40160 30160 20160 10160 dn l e r ro r ( l s b ) d ac co d e t a = 2 5 c v dd = 5 v , v ref = 4 . 096v figure 6. typic a l d n l p l ot 04 76 2- 00 7 ?40 ?20 0 2 0 4 0 6 0 8 0 1 00 120 ?1 . 2 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 140 dn l e r ro r ( l s b ) t e m per a t u r e ( c ) v dd = 5 . 5 v , v re f = 4. 096 v v dd = 2 . 7 v , v re f = 2. 0v m a x dn l e rro r @ v dd = 2. 7v m a x d n l e r ro r @ v dd = 5. 5v m i n dn l e r r o r @ v dd = 2. 7v m i n dn l e r r o r @ v dd = 5. 5v figure 7. dnl vs. t e mpe r atur e 04 76 2- 00 8 ?40 ?20 0 2 0 4 0 6 0 8 0 1 00 120 ?1 . 2 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 140 t u e e r r o r ( m v) t e m per a t u r e ( c ) v dd = 5 . 5 v , v re f = 4. 096 v v dd = 2 . 7 v , v re f = 2. 0v ma x t u e e r r o r @ v dd = 2. 7v m a x t u e e rro r @ v dd = 5. 5v m i n t u e e r ro r @ v dd = 5. 5 v m i n t u e e rro r @ v dd = 2. 7v figure 8. tue vs. te mpe r atur e 04 76 2- 09 0 ?40 ? 2 0 0 20 40 60 8 0 100 1 2 0 ?1. 6 ?1. 4 ?1. 2 ?1. 0 ?0. 8 ?0. 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 140 i n l e rro r ( l s b ) t e mp er a t u r e ( c ) v dd = 5 . 5 v , v re f = 4. 096 v v dd = 2 . 7 v , v re f = 2. 0v ma x i n l er r o r @ v dd = 2. 7v ma x i n l er r o r @ v dd = 5. 5v m i n i n l e r ro r @ v dd = 5. 5v m i n i n l e rro r @ v dd = 2. 7 v figure 9. inl vs. tem p er a t ure
ad5061 r e v. a | pa ge 9 o f 2 0 04 76 2- 01 0 2. 0 ?1 . 6 ?1 . 4 ?1 . 2 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 5. 5 5. 0 4. 5 4. 0 3. 5 3. 0 2. 5 dn l e r ro r ( l s b ) re f e r e nce v o l t a g e ( v ) m a x dn l e rro r @ v dd = 5. 5v m i n dn l e r r o r @ v dd = 5. 5v t a = 25 c figure 1 0 . d n l v s . r e feren ce i n put vo ltage 04 76 2- 0 1 1 2. 0 ?1. 2 ?1. 0 ?0. 8 ?0. 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 5. 5 5. 0 4. 5 4. 0 3. 5 3. 0 2. 5 t u e e r r o r ( m v) re f e r e nc e v o l t ag e ( v ) ma x t u e er r o r @ v dd = 5. 5v m i n t u e e rro r @ v dd = 5. 5v t a = 25 c figure 11. tue vs. r e fere nce input volt age 04 76 2- 00 9 2. 0 ?1 . 6 ?1 . 4 ?1 . 2 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 5. 5 5. 0 4. 5 4. 0 3. 5 3. 0 2. 5 i n l e rro r ( l s b ) re f e r e nce v o l t a g e ( v ) m a x i n l er r o r @ v dd = 5. 5v m i n i n l e rro r @ v dd = 5 . 5v t a = 25 c figure 12. inl vs. refere nce input volt age 04 76 2- 01 3 ?40 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1. 0 1. 1 1. 2 1. 3 1. 4 1. 5 140 120 100 80 60 40 20 0 ?20 s u p p l y cur re n t ( m a ) t e m p e r a t ure ( c) v dd = 5 . 5 v , v re f = 4. 096v v dd = 2 . 7 v , v re f = 2. 0v co d e = f u l l - s cal e v dd = 5. 5 v v dd = 2 . 7v figure 1 3 . supp ly c u rre nt v s . te mper a t ure 04 76 2- 01 4 0 0 3. 0 0 2. 7 5 2. 5 0 2. 2 5 2. 0 0 1. 7 5 1. 5 0 1. 2 5 1. 0 0 0. 7 5 0. 5 0 0. 2 5 70 000 6 0000 5 0000 4 0000 3 0000 20000 10000 s u p p l y cur re n t ( m a ) dac c o de v dd = 3 . 0 v , v re f = 2. 5v v dd = 5 . 5 v , v re f = 4. 096v t a = 25 c figure 1 4 . supp ly c u rre nt vs. digit a l in put code 04 76 2- 01 5 2. 5 0 2. 0 1. 8 1. 6 1. 4 1. 2 1. 0 0. 8 0. 6 0. 4 0. 2 6. 0 5. 5 5. 0 4. 5 4. 0 3. 5 3. 0 s u p p l y cur re n t ( m a ) su p p l y vol t a g e ( v ) v ref = 2. 5v t a = 2 5 c c o d e = m i ds cal e figure 1 5 . supp ly c u rre nt v s . supply v o ltag e
ad5061 rev. a | page 10 of 20 04 76 2- 01 2 ?40 ?0. 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 0. 8 1. 0 1. 2 1. 4 1. 6 1. 8 140 120 100 80 60 40 20 0 ?20 o f f s e t e r ro r ( m v ) t e m p e r a t ure ( c) v dd = 5 . 5 v , v re f = 4. 096v v dd = 2 . 7 v , v re f = 2. 0v o f f s e t e rro r @ v dd = 5. 5v o f f s et er r o r @ v dd = 2. 7v figure 1 6 . offset v s . te mper atur e 0 476 2- 0 1 7 c h 2 5 0 m v /d iv c h 1 2 v /d iv t i m e b a s e 4 0 0 n s / d i v 24t h cl o c k f al l i n g ch1 = s c l k ch 2 = v ou t fig u re 1 7 . d i g i t a l-t o -a na log g lit ch i m puls e; s ee f i g u r e 2 1 0 50 10 0 15 0 20 0 25 0 30 0 100 0 100 00 10 0000 10000 00 f r e q ue nc y ( h z ) no i s e s p e ct ra l d e n s i t y ( n v / hz ) v dd = 5 v t a = 25 c v ref = 4. 09 6v f u l l - s cal e m i ds cal e z e ro - s cal e 100 04 76 2- 01 8 figure 18. output nois e spectral d e n s ity 04 76 2- 0 1 9 ch 2 2 v / di v ch1 2v / d i v t i m e ba s e = 5. 0 0 s ch3 2v ch 2 = v ou t ch1 = t r i g g e r ch3 = s c l k figure 19. exiting powe r-down t i me t o mids cale 04 76 2- 0 2 0 v dd = 3 v dac = f u l l - s cal e v ref = 2. 7v t a = 25 c y a xi s = 2 v/ d i v x a x i s = 4s/ di v fi gur e 20 . 0 . 1 hz to 1 0 hz no i s e pl o t 04 76 2- 02 1 50 100 1 5 0 200 250 30 0 350 400 450 500 0 sa m p l e s am p l i t ude ( 200 v / di v ) v dd = 5v v re f = 4. 096 v t a = 2 5 c 10n s/ s a m p l e fi gure 21 . g l i t ch en ergy
ad5061 rev. a | page 11 of 20 04 76 2- 02 2 ?40 ?20 ?0. 10 0. 1 0 0. 0 8 0. 0 6 0. 0 4 0. 0 2 0 ?0. 02 ?0. 04 ?0. 06 ?0. 08 140 120 100 80 60 40 20 0 g a i n e rro r ( % f s r) t e m p e r a t ure ( c) v dd = 5 . 5 v , v re f = 4. 096v v dd = 2 . 7 v , v re f = 2. 0v g a i n e rro r @ v dd = 2 . 7v g a i n e rro r @ v dd = 5. 5v figure 2 2 . g a i n e r r o r v s . t e mp er ature 04 76 2- 02 3 0. 83 0. 84 0. 85 0. 86 0. 87 0. 88 0. 89 0. 90 0. 91 0 16 14 12 10 8 6 4 2 mo r e fr e q u e n c y bi n figure 23. i dd his t o g ra m @ v dd = 3 v 04 76 2- 02 4 1. 00 1. 01 1. 02 1. 03 1. 04 1. 05 1. 06 1. 07 1. 08 1. 0 9 1. 1 0 1. 1 1 0 14 12 10 8 6 4 2 mor e fr e q u e n c y bi n figure 24. i dd his t o g ra m @ v dd = 5 v 04 762 - 0 2 5 ch1 2v / d i v ch2 1 v / d i v t i m e b a s e = 100 s v dd = 5 v v re f = 4. 096v dd ra m p ra t e = 200 s t a = 25 c ch1 = v dd ch2 = v ou t figure 2 5 . ha rdw a r e p o we r-d o wn g l itch 0 476 2- 0 2 6 c h 1 2 v /d iv c h 2 2 v / d i v c h 3 2 0 m v / d i v c h 4 2 v /d iv t i m e bas e 1 s / di v ch3 = v ou t ch 4 = t r i g g e r ch 2 = s y nc ch1 = s c l k v dd = 5 v v re f = 4. 096v dd t a = 25 c figure 26. exiting s o ftwar e pow er-d own glitch 04 76 2- 09 1 2. 7 2 . 9 3. 1 3 . 3 3. 5 3 . 7 3. 9 4 . 1 4. 3 4 . 5 4 . 7 4 . 9 5. 1 0 0. 5 0 0. 4 5 0. 4 0 0. 3 5 0. 3 0 0. 2 5 0. 2 0 0. 1 5 0. 1 0 0. 0 5 5. 5 5. 3 he adro o m ( v ) re f e r e nc e v o l t ag e ( v ) figure 27. v dd he a d ro om v s . r e fere nc e vo ltage.
ad5061 rev. a | page 12 of 20 5. 05 5. 00 4. 95 4. 90 4. 85 4. 80 4. 75 4. 70 4. 65 4. 60 4. 55 4. 70 4 . 72 4. 74 4. 76 4 . 78 4. 80 4. 82 4. 84 4. 86 4. 8 8 4. 90 4. 92 4. 9 4 4. 96 4. 98 5 . 00 04 762 - 0 4 2 dac o u t p u t ( v ) v re f (v) v dd = 5 . 0 v t a = 2 5 c dac = f u l l - s cal e figure 2 8 . typ i c a l output voltag e v s . r e feren ce v o lt age 5 . 005 4 . 975 4 . 980 4 . 985 4 . 990 4 . 995 5 . 000 5. 50 5. 00 5. 05 5. 10 5. 15 5. 2 0 5. 2 5 5. 30 5. 3 5 5. 4 0 5. 4 5 04 762 - 0 6 5 dac o u t p u t ( v ) v dd (v ) v ref = 5 v t a = 25 c fig u re 2 9 . ty p i c a l out p ut v o lt ag e v s . supply v o lt ag e 04 76 2- 04 7 ch 4 50. 0m v m 4. 00 s ch1 1. 6 4 v c4 = 143mv p - p 1k ? to g n d z e ro - s cal e figure 3 0 . typ i c a l glitch upo n e n ter i n g softwa re po wer- down to z e ro-s ca l e 04 76 2- 04 8 ch 4 20. 0m v m 1. 00 s ch1 1. 6 4 v c4 = 50mv p - p 1k ? t o g n d z er o - sc a l e fig u re 3 1 . ty p i c a l glit ch upo n e x it ing sof t wa re p o we r-d o wn t o z e r o -sc a le 04 76 2- 04 9 c h 3 2 . 0 0 v c h 2 5 0 m v m 1 .0 0 m s c h 3 1 . 3 6 v 2 c2 25 m v p - p c3 4 . 96v p - p c3 f a l l 9 35. 0 s c3 r i s e s no v a l i d ed g e 3 t t fig u re 3 2 . ty p i c a l glit ch upo n e x it in g ha rdw a re p o w e r- down to t h re e stat e 04 76 2- 05 0 c h 3 2 . 0 0 v c h 2 5 0 m v m 1 .0 0 m s c h 3 1 . 3 6 v 2 c2 30 m v p - p c3 4 . 96v p - p c3 f a l l s no v a l i d ed g e c3 r i s e 9 46. 2 s 3 t t figure 3 3 . typ i c a l glitch upo n e n ter i n g ha rdw a re p o we r - down to z e ro-s ca le
ad5061 rev. a | page 13 of 20 0 . 0010 0 . 0008 0 . 0006 0 . 0004 0 . 0002 0 ?0. 00 02 ?0. 00 04 ?0. 00 06 ?0. 00 08 ?25 ?2 0 ?15 ?10 ?5 0 5 10 15 2 0 25 30 04 76 2- 05 1 ? vo l t a g e ( v ) c urre n t ( m a) co de = m i ds cal e v dd = 5 v , v re f = 4. 0 96v v dd = 3 v , v re f = 2 . 5v v dd = 5. 5 v v dd = 3 v figure 34. typ i cal output load r e gulation 0. 1 0 ?0 . 1 0 ?0 . 0 8 ?0 . 0 6 ?0 . 0 4 ?0 . 0 2 0 0. 0 2 0. 0 4 0. 0 6 0. 0 8 ? 2 5 ?20 ?15 ?1 0 ? 5 0 5 1 0 1 5 2 0 2 5 3 0 04 762 - 0 6 3 ? v ou t (v ) i ou t (m a ) co de = m i ds ca l e v dd = 5 v , v re f = 4 . 096v v dd = 3 v , v re f = 2. 5 v v dd = 3 v , v re f = 2 . 5 v v dd = 5 v , v re f = 4. 096 v figure 3 5 . typ i c a l c u rre nt li miti ng p l o t 2. 1 1. 0 1. 1 1. 2 1. 3 1. 4 1. 5 1. 6 1. 7 1. 8 1. 9 2. 0 ?10 s 9 . 96 s 8 s 6 s 4 s 2 s 0 ?2 s ?4 s ?6 s ?8 s 04 76 2- 05 2 v dd = 5. 5v v ref = 4. 096v 10% t o 90% r i s e t i m e = 0. 688 s sl e w r a t e = 1. 16 v/ s da c ou tp u t 1. 04v 2. 04v figure 36. typ i cal output slew rate
ad5061 rev. a | page 14 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 4. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical ad5061 dnl vs. code plot is shown in figure 6. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5061 because the output of the dac cannot go below 0 v. this is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. tot a l un a dju s te d e r ror ( t u e ) total unadjusted error is a measure of the output error taking all the various errors into account. a typical tue vs. code plot is shown in figure 5. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition; see figure 17 and figure 21. the expanded view in figure 17 shows the glitch generated following completion of the calibration routine; figure 21 zooms in on this glitch. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and measured with a full-scale code change on the data bus; that is, from all 0s to all 1s, and vice versa.
ad5061 rev. a | page 15 of 20 theor y of opera tion the ad5061 is a sin g le 16 -b i t , s e r i al in p u t, v o l t a g e o u t p u t d a c. i t o p era t es f r o m s u p p l y v o l t a g es o f 2.7 v t o 5.5 v . da ta is wr i t - t e n t o t h e ad50 61 in a 24 -b i t wo r d f o r m a t , via a 3-wir e s e r i a l in t e r f ace . the ad5061 inco r p o r a t es a p o w e r - o n r e s e t circ ui t tha t ens u r e s t h e d a c ou tp ut p o we r s up to z e ro - s c a l e or m i d s c a l e . t h e de vice a l s o has a s o f t wa r e p o we r - do wn mo de pin t h a t r e d u ce s t h e typ i ca l c u r r en t co nsum p t ion t o less t h an 1 a. dac architecture the d a c a r c h i t ec t u r e o f t h e ad5061 co n s is ts o f tw o ma t c h e d d a c s e c t io n s . a sim p l i f i e d circ ui t di a g ra m is sho w n i n f i gur e 37. t h e fo ur ms bs o f t h e 16-b i t da t a w o rd a r e de co de d t o dr i v e 15 s w i t c h es, e1 t o e15. e a c h o f th es e s w i t ch es co nn ec ts one of 1 5 m a tc h e d re s i stor s to e i t h e r d a c g n d or v ref bu f f e r output . th e r e ma ini n g 12 b i ts o f t h e da t a w o rd dr i v e s w i t ch es s0 t o s11 o f a 12-b i t v o l t a g e mo de r - 2r l a dder n e tw o r k. 2r 04 776 2- 0 2 7 s0 v re f 2r s1 2r s1 1 2r e1 2r e2 2r e1 5 2r v ou t 12- bi t r - 2r l adde r f o ur m s bs de co de d i n to 1 5 eq u a l seg men t s figure 3 7 . da c l a d d er stru cture reference buffer the ad5061 op era t es wi t h an ext e r n al r e f e r e n c e . th e r e f e r e n c e in p u t (v ref ) has a n in p u t ra n g e o f 2 v t o v dd ? 50 mv . this in p u t v o l t a g e is t h e n us e d t o p r o v i d e a b u f f er e d r e fer e n c e fo r t h e da c c o r e . serial interface the ad5061 has a 3-wir e s e r i a l in t e r f ace ( sy n c , sclk, an d d i n), which is co m p a t i b le wi th s p i, qs p i , and mi cr o w ire in t e r f ace st a n d a r d s, as w e l l as most ds p s . s e e f i gur e 2 fo r a t i mi n g d i a g ra m o f a ty p i c a l wr i t e s e q u e n ce. the wr i t e s e q u e n ce b e g i n s b y b r in g i n g t h e sy n c lin e lo w . d a t a f r o m t h e d i n li n e is clo c k e d i n to t h e 24- b i t sh if t r e g i st er o n t h e fa l l in g e d ge o f s c lk. the s e r i a l clo c k f r e q uen c y ca n b e as hi g h as 30 mh z, m a k i n g t h es e p a r t s co m p a t i b le w i t h hig h sp e e d ds p s . on t h e 2 4 t h fal l i n g c l o c k e d g e , t h e las t da t a b i t is c l o c k e d in and t h e p r og ra mm e d f u n c t i o n is exe c u t e d ( t ha t is, a cha n ge in t h e d a c r e g i s t er co n t e n ts a nd/o r a cha n ge i n t h e m o de o f op e r a t i o n ) . at t h i s s t a g e , t h e sy n c lin e ma y be kep t lo w o r be b r o u g h t h i gh. i n e i th e r ca se , i t m u s t be b r o u gh t h i gh f o r a m i n i m u m o f 12 n s bef o r e t h e n e xt wr i t e s e q u en c e s o tha t a fa l l in g edg e o f sy n c ca n i n i t i a t e t h e n e xt wr i t e s e q u en c e . b e c a us e t h e sy n c b u f f er dra w s mo r e c u r r en t w h e n v ih = 1.8 v tha n i t do es when v ih = 0.8 v , sy n c s h ou ld be idle d lo w be tw e e n wr i t e s e q u ences f o r a n ev en lo wer p o w e r o p era t io n o f the p a r t . a s p r e v io us l y indi ca te d , h o w e ver , i t m u st b e b r o u g h t hi g h a g ain j u st b e fo r e t h e n e xt wr i t e s e q u ence . inpu t shift register the in p u t s h if t r e g i s t er is 24 b i ts wide; s e e f i gu r e 38. p d 1 an d p d 0 a r e co n t r o l b i ts tha t con t r o l which m o de o f o p era t io n t h e p a r t i s i n ( n or m a l mo d e or a n y one of t h re e p o we r - d o w n m o des). t h er e i s a m o r e co m p l e te de s c r i p t ion o f t h e va r i o u s m o des i n t h e p o w e r - d o w n m o des s e c t io n. th e n e xt 16 b i ts a r e t h e da t a b i ts. thes e a r e t r a n sfer r e d t o t h e d a c reg i s t er o n t h e 24th fal l i n g e d g e o f sclk. sync interrupt i n a n o rm al w r i t e seq u en ce , t h e sy n c line is k e p t l o w f o r a t le ast 24 fa l l i n g e d ges o f sclk and t h e d a c is up d a te d o n t h e 24th fal l i n g e d g e . h o wev e r , if sy n c is b r o u g h t hig h bef o r e the 24th fal l i n g e d g e , this ac ts as a n in t e r r u p t t o t h e wr i t e s e q u ence . the s h if t r e g i s t e r is r e s e t a nd t h e wr i t e s e q u e n c e is s e en as in valid . n e i t her a n u p da t e o f t h e d a c r e g i s t er co n t en ts n o r a cha n g e i n t h e op era t i n g m o de o c c u rs; s e e f i gu r e 41. da t a b i t s db 15 ( m sb) db0 ( l s b ) d1 5 d 14 d 1 3 d 1 2 d 1 1 d 10 d9 d 8 d 7 d6 d 5 d 4 d3 d2 d1 d 0 no r m a l o p e r a t i o n 1k ? to g n d 100 k ? to g n d 3-s t a t e p o w e r- do w n m o des 0 0 1 1 0 1 0 1 04 762- 02 8 00 0 0 0 0 p d 1 p d 0 fi gure 38 . inp u t regi ster contents
ad5061 rev. a | page 16 of 20 power-on to zero-scale or midscale the ad5061 con t a i n s a p o w e r - o n r e s e t cir c u i t tha t con t r o ls the o u t p ut v o l t a g e d u r i n g p o w e r - u p . the d a c r e g i st er is f i l l e d w i t h t h e zer o -s cale or mids c a le co de a nd t h e o u t p u t v o l t a g e is zer o - s c ale o r mids c a l e . i t r e ma in s t h e r e un t i l a vali d wr i t e s e q u ence i s made t o t h e d a c. this is us ef u l in a p plic a t io n s w h er e i t is im p o r t an t t o k n o w t h e st a t e o f t h e o u t p ut o f t h e d a c w h i l e i t is in t h e p r o c es s of p o w e r i n g u p . software reset t h e devi c e c a n be p u t in t o so f t w a r e r e se t b y set t in g all b i t s i n th e d a c r e g i s t er t o 1; this in c l u d es wr i t ing 1s to b i t d23 t o bi t d16, w h ich i s n o t t h e n o r m a l m o de o f o p era t io n. n o t e t h a t th e sy n c in ter r u p t c o mma nd can n ot b e p e r f o r m e d if a s o f t w a re re s e t c o m m a n d i s s t ar te d. power-down modes the ad5061 con t a i n s f o ur s e p a ra t e m o des o f o p era t ion. th es e mo d e s are s o f t w a re - p ro g r am m a bl e b y s e tt i n g t w o bit s ( d b 1 7 a nd d b 16) in t h e co n t r o l r e g i s t e r . t a b l e 6 sh o w s h o w t h e s t a t e of t h e bit s c o r r e s p o nd s to t h e m o d e of op e r a t i o n of t h e d e v i c e . table 6. modes of operation d b 1 7 d b 1 6 o p er a t i n g mod e 0 0 nor m a l opera ti o n p o w e r - do w n m o d e : 0 1 3-sta t e 1 0 100 k ? to gnd 1 1 1 k ? to gnd w h en b o t h b i ts a r e s e t t o 0, t h e p a r t w o rks n o r m al l y wi t h i t s nor m a l p o we r c o nsu m pt i o n . h o we ve r , for t h e t h re e p o we r - down mo de s , t h e su p p ly c u r r e n t f a l l s to l e ss t h an 1 a a t 5 v (265 na a t 3 v). n o t o n l y do es t h e su p p l y c u r r en t fal l , b u t t h e output st age i s a l s o i n te r n a l ly s w itc h e d f r om t h e output of t h e am pl i f i e r to a re s i stor ne t w or k of k n ow n v a lu e s . t h i s h a s t h e ad van t a g e t h a t t h e o u t p ut i m p e dan c e o f t h e p a r t is kno w n w h i l e t h e p a r t is i n p o w e r - do w n m o de . th er e a r e t h re e dif f er en t opt i ons . t h e output i s c o n n e c te d i n te r n a l ly to g n d t h rou g h a 1 k? r e sis t o r o r a 100 k? r e sis t or , o r i t is lef t o p en-cir c u i t e d ( 3 -st a te ) . t h e ou t p ut st age is i l lu st r a te d in fig u re 3 9 . p o w e r- do w n ci rcu i t r y a d 5061 dac 04 76 2- 0 2 9 v ou t re s i s t o r ne t w o r k ou t p u t buf f e r figure 39. output s t age du ring powe r - down the b i as g e n e ra t o r , t h e d a c cor e a nd o t h e r as s o ci a t e d li n e a r cir c ui t r y a r e a l l sh u t do w n w h e n t h e p o w e r - do w n m o de is a c ti v a t e d . h o w e v e r , th e co n t en ts o f th e d a c r e gi s t e r a r e un a f f e ct ed w h en in po w e r - d o wn . th e t i m e t o exi t po w e r - d o wn is typ i c a l l y 2.5 s f o r v dd = 5 v , a nd 5 s f o r v dd = 3 v ; s e e f i gur e 19. microprocessor interfacing ad5061-to-adsp-2101/adsp-2103 interface f i gur e 40 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5061 a nd t h e ads p -2101/ads p -2103. the ad s p -2101 /ads p - 2103 sh o u ld b e s e t u p t o o p e r a t e i n t h e s p or t t r a n smi t al t e r n a t e f r a m in g m o de . the ads p -2101/ads p -2 103 s p o r t is p r og ra mm ed t h rou g h t h e sp or t c o n t ro l re g i ste r an d s h ou l d b e c o n f i g u r e d as fol l o w s: in t e r n a l clo c k o p era t io n, ac t i ve lo w f r a m ing, 16-b i t w o r d len g t h . t r a n smissio n is in i t ia t e d b y wr i t ing a w o r d t o t h e tx r e g i s t er a f t e r t h e spo r t has b e e n ena b le d . a d 5061 1 add i t i o na l p i ns o m i t t e d f o r cl ari t y tf s dt sc l k sy n c di n sc l k 04 762 - 0 3 0 a d s p - 2 101/ a d s p - 21 03 1 fi gur e 40 . ad5 061 -to - adsp -210 1/ adsp -21 0 3 int e r f ac e 04 76 2- 03 1 db2 3 db2 3 d b 0 db 0 i n v a l i d w r i t e se q u en c e : s y n c hi g h be f o re 2 4 th fa l l i n g e d g e v a l i d w r i t e se q u en c e , o u t p u t u p d a t es on th e 2 4 th f a lli n g e d ge syn c sc l k di n figure 41. sync interrup t fa ci li ty
ad5061 rev. a | page 17 of 20 ad5061-to-68hc11/68l1 1 interface f i gur e 42 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5061 a nd t h e 68h c11/68l11 micr o c o n tr ol ler . sck o f t h e 68 h c 11/68l11 dr i v es t h e scl k p i n o f the ad5061, while t h e m o s i o u t p u t dr i v es t h e s e r i al da t a l i n e o f t h e d a c. the sy n c sig n al is der i ve d f r o m a p o r t line (pc7). the s e t-u p condi t i on s fo r co r r e c t o p era t ion o f t h is i n t e r f ace r e q u ir e t h a t t h e 68 h c 11/ 68l11 be co nf ig ur ed s o tha t i t s cpo l b i t is 0 and i t s cp h a b i t is 1. w h en da t a is bein g tra n smi t t e d t o t h e d a c , th e sy n c lin e is tak e n lo w (p c7). w h en t h e 68h c11/68l11 is co nf igur ed w h er e i t s cpol b i t is 0 and i t s cph a b i t is 1, d a t a a p p e a r in g o n th e m o s i ou t p u t is valid o n t h e fal l in g e d g e o f sck. s e r i al da t a f r o m th e 68h c11/68l11 is tra n smi t t e d in 8-b i t b y t e s wi th only e i gh t fallin g c l o c k ed g e s occurr i n g in t h e tra n sm i t c y c l e . da t a is tra n smi t t e d ms b f i rs t. t o lo ad da ta t o the ad5 061, pc7 is lef t l o w af te r t h e f i r s t e i g h t b i t s are t r ans f e r re d, a s e c o n d s e r i a l w r i t e o p er a t ion is p e r f o r m e d to t h e d a c, a nd pc7 is t a k e n hig h a t th e e n d o f th i s p r oced ur e . a d 5061 1 1 add i t i o na l p i ns o m i t t e d f o r cl ari t y pc 7 sc k mo s i sy n c sc l k di n 0 476 2- 0 3 2 68 h c 1 1 / 68 l 1 1 1 fig u re 4 2 . a d 50 6 1 -t o-68 hc 11 /6 8l1 1 i n t e rf ac e ad5061-to-blackfin? a d sp-bf53x interface f i gur e 43 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5061 a nd t h e b l ac kf in ads p -53x micr o p r o ces s o r . th e ads p -b f53x p r o c es - s o r f a m i ly i n c o r p or a t e s t w o du a l - c h a n n e l s y nch r onou s s e r i a l p o r t s, s p or t1 a nd s p or t0, fo r s e r i a l and m u lt i p r o cess o r co mm unic a t io ns. u s in g s p o r t0 t o co nn ec t t o th e ad5061, t h e s e t u p fo r t h e in t e r f ace is: dt0p ri dr i v es t h e d i n p i n o f th e ad5061, w h ile tscl k0 dr i v es t h e scl k of th e p a r t ; t h e sy n c is dr i v en f r o m tfs0. ads p - b f 5 3 x 1 a d 5 061 1 1 add i t i o na l p i ns o m i t t e d f o r cl ari t y dt 0p ri ts c l k 0 tf s 0 di n sc l k sy n c 0 476 2- 0 3 3 fi gur e 43 . ad5 061 -to - bla c kfi n adsp -bf5 3 x inte r f ac e ad5061-to-80c51/80l5 1 interface f i gur e 44 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5061 a nd t h e 80c51/80l51 micr o c o n tr ol ler . the s e t u p f o r the in t e r f ace is: txd o f t h e 80c51/80l51 dr i v es sclk o f t h e ad5061 while rxd dr i v es t h e s e r i al da t a li n e o f t h e p a r t . th e sy n c sig n al is a g a i n der i ve d f r o m a b i t - p r o g r a mma b l e pin on t h e p o r t . i n t h is cas e , p o r t l i n e p3.3 is us e d . w h e n da t a is t o b e t r a n smi t t e d t o th e ad5061, p3 .3 is tak e n lo w . the 80c51/80l 51 tra n smi t s da t a o n ly in 8- b i t b y tes; t h us o n ly eig h t fa l l i n g clo c k e d ges o c c u r i n th e tra n sm i t c y c l e . t o loa d da t a t o th e d a c , p3.3 i s le ft lo w a f t e r t h e f i rst eig h t b i ts a r e t r a n smi t t e d , an d a s e cond wr i t e c y cle is i n i t i a te d to t r ans m i t t h e s e c o nd b y te of da t a . p 3 . 3 i s t a ke n h i g h f o l l o w in g t h e com p letio n o f t h is c y c l e . th e 80c51/80l51 o u t - p u t s th e se ri al d a t a i n a f o rm a t th a t h a s th e l s b fi r s t . t h e ad5061 r e q u ir es i t s da ta wi th t h e ms b as t h e f i rs t b i t r e cei v e d . the 8 0 c51 / 80 l 51 tr a n smi t r o u t ine sh ou l d ta k e t h is in t o ac co u n t. 80 c 5 1/ 80l 5 1 1 a d 5061 1 1 add i t i o na l p i ns o m i t t e d f o r cl ari t y p3 . 3 tx d rxd sy n c sc l k di n 0 476 2- 0 3 4 fig u re 4 4 . a d 50 6 1 -t o-80c 5 1 / 80l 51 int e rf a ce ad5061-to-microwire interface f i gur e 45 sh o w s a n in t e r f ac e b e tw een t h e ad50 61 a nd an y mi cro w ire- co m p a t i b le de vi ce. s e r i a l da t a is shif te d o u t on t h e fal l i n g e d g e o f t h e s e r i al clo c k an d is clo c k e d in t o t h e ad5061 o n t h e r i sin g edg e o f t h e s k . mi cro w i re 1 a d 5 061 1 1 add i t i o na l p i ns o m i t t e d f o r cl ari t y cs sk so sc l k di n 04 76 2- 03 5 sy n c fi gur e 45 . ad5 061 -to - microw ire inter f a c e
ad5061 rev. a | page 18 of 20 appli c a t ions choosing a reference t o ac hiev e t h e op tim u m p e r f o r ma n c e f r o m the ad5061, t h ou g h t s h ou l d b e g i ve n to t h e choi c e of a pre c i s i o n vo lt age r e f e r e n c e . th e ad5061 has j u st o n e r e f e r e nce in p u t, v ref . th e v o l t a g e o n t h e r e fer e n c e i n p u t is us e d t o s u p p l y t h e p o si t i v e in p u t t o t h e d a c. th er efo r e , a n y er r o r in t h e r e fer e n c e is re f l e c te d i n t h e d a c . ther e a r e fo ur p o s s i b le s o ur ces o f er r o r w h en ch o o sin g a v o l- t a ge r e fer e n c e fo r hig h acc u rac y a p plica t io n s : i n i t ia l acc u rac y , p p m dr if t, lo n g - t er m dr if t, an d o u t p ut v o l t a g e n o is e. i n i t ia l a c c u r a c y on t h e output vo lt age of t h e d a c l e a d s to a f u l l - s c a l e er r o r in t h e d a c. t o minimi ze t h es e er r o rs, a r e fer e n c e wi t h hig h in i t ia l acc u rac y is p r e f er r e d . als o , ch o o sing a r e fer e n c e wi th an o u t p u t t r im ad j u s t m e n t , s u c h as t h e ad r43x fa mil y , al lo ws a sys t e m desig n er t o tr im o u t sys t em er r o rs b y s e t t in g a r e fer e n c e v o l t a g e t o a v o l t a g e o t h e r t h an t h e n o minal . th e t r i m ad j u s t m e n t can als o b e us e d a t t h e op era t i n g t e m p era t ur e t o tri m o u t a n y e r r o r s . b e ca us e t h e s u p p l y c u r r en t r e q u ir ed b y the ad5 061 is ext r em e l y lo w , t h e p a r t s a r e ide a l fo r lo w s u p p l y a p plica t io n s . the ad r395 v o l t a g e r e f e r e n c e is r e co mm ended. this r e q u ir es les s tha n 100 a o f q u ies c en t c u r r en t a nd can, th er ef o r e , dr i v e m u l t i p le d a cs i n o n e sy st em , if r e q u ir e d . i t a l s o p r o v ides ver y g o o d no is e p e r f o r manc e a t 8 v p-p in t h e 0. 1 h z t o 1 0 h z r a n g e. ad5 06 1 sy n c sc l k di n 7v 5v v ou t = 0v to 5v ad r 3 9 5 0 476 2- 0 3 6 3- w i re se r i al in te r f ace fi gur e 46 . adr395 a s re fe re nce to the ad5 0 6 1 l o n g - t er m dr if t is a me as ur e o f h o w m u ch t h e refer e n c e dr if ts o v er t i m e . a r e fer e n c e w i t h a t i g h t lo n g -t er m d r if t sp e c if ic a t ion e n su re s t h at t h e o v e r a l l s o lut i on re m a i n s re l a t i v e ly st abl e d u r i n g i t s e n t i r e lifet i me . th e tem p era t ur e co ef f i cien t of a r e fer e n c e s o u t p u t v o l t a g e af f e c t s inl, d n l , a nd tue. a r e f e r e n c e wi t h a t i g h t t e m p era t u r e co ef f i cien t sp e c if ica t ion sh o u ld b e ch os en t o r e d u ce t e m p er a t ur e de p e n d e n c e o f t h e d a c o u t p u t v o l t a g e on amb i e n t c o nd i t i o ns . i n h i g h acc u rac y a p plica t io n s , w h ich ha ve a r e l a t i ve ly lo w n o is e b u d g e t , re fe re nc e output vo lt age noi s e ne e d s to b e c o ns i d e r e d . i t is im p o r t an t t o ch o o s e a r e fer e n c e w i t h as lo w a n o u t p u t n o is e v o l t a g e as p r ac t i cal fo r t h e sys t e m n o is e r e s o l u t i o n r e q u ir e d . p r e c isio n v o l t a g e r e fer e n c es, s u ch as t h e adr43 5 , p r o d uce lo w o u t p u t n o is e in th e 0.1 h z t o 10 h z r e g i on. t a b l e 7 sh o w s e x a m ples o f r e co mmende d p r e c isio n r e fer e n c es f o r us e as a s u p p l y t o th e ad50 61. table 7. precision r e fere nces part list for the ad5061 pa r t n o . initial acc u ra c y (mv ma x) t e mper a t ur e d r if t (p pm/c ma x) 0.1 hz t o 10 hz noise (v p - p t y p) a d r 4 3 5 2 3 (so - 8 ) 8 adr425 2 3 (so - 8) 3.4 a d r 0 2 3 3 (so - 8 ) 1 0 a d r 0 2 3 3 ( s c 7 0 ) 1 0 a d r 3 9 5 5 9 ( t so t - 2 3 ) 8 bipolar operation the ad5061 has been desig n e d f o r sin g le-s u p p l y o p era t io n, b u t a b i p o la r o u t p u t ra n g e is also p o s s i b le usin g t h e cir c ui t sho w n in f i gur e 47. th e c i r c ui t sho w n yi elds a n o u t p u t v o l t a g e ra n g e o f 5 v . r a i l - t o-ra i l o p era t ion a t t h e am plif ier o u t p u t is achi e v ab l e usin g a n ad86 75/ad820 /ad8 032 o r a n o p 196/o p 295. the o u t p u t v o l t a g e fo r a n y in p u t co de ca n b e ca lc u l a t e d as fol l o w s: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = 1 r 2 r v 1 r 2 r 1 r d v v dd dd o 65536 w h er e d r e p r es en ts t h e in p u t c o de in dec i mal (0 t o 65536). wi t h v ref = 5 v , r1 = r2 = 10 k?, v 5 65536 10 ? ? ? ? ? ? ? = d v o this is an ou t p u t v o l t a g e r a n g e of 5 v wi t h 0x 0 000 co r r esp o nd- i n g to a ? 5 v output a n d 0 x f f f f c o r r e s p o nd i n g to a + 5 v out p ut . a d 5061 +5 v 10 f 04 76 2- 03 7 r1 = 10k ? v bf v ou t v re f 0. 1 f 3- w i re ser i a l in te r f a c e a d 82 0/ op2 9 5 + ? ?5 v +5 v r2 = 10k ? 5 v fi gur e 47 . bi pola r ope r a t i o n wi th the ad5 061
ad5061 rev. a | page 19 of 20 using a galvanically-isolated interface chip i n p r o c es s con t rol a p p l ica t io n s in ind u s t r i al en vir o n m e n t s, i t is of te n ne c e ss ar y to u s e a g a lv an i c a l ly - i s o l a te d i n te r f a c e to prote c t an d i s o l a t e t h e c o n t ro l l i n g c i rc u i t r y f rom an y h a z a rd ou s co mm on- m o d e v o l t a g es t h a t ma y o c c u r in t h e a r e a w h er e t h e d a c is f u n c t i oning. i co u p l e r ? p r o v ide s is ola t i o n in excess o f 2.5 kv . b e ca us e th e ad5061 us es a 3-wir e s e r i a l log i c in t e r f ac e , th e adum130x fa mil y p r o v ides a n ideal dig i t a l s o l u tio n f o r th e da c i n t e r f a c e . the ad um130 x is ola t o r s p r o v i d e t h r e e i n de p e n d en t i s ola t io n c h a nne ls in a var i ety o f c h a n n e l co nf igura t io n s a n d da t a ra t e s . the y o p er a t e ac r o s s t h e f u l l r a ng e f r om 2.7 v t o 5.5 v , p r o v i d ing c o m p a t ibi l it y w i t h l o we r volt age s y ste m s a n d e n abl i ng a volt age tra n s l a t i o n fun c ti o n ali t y a c r o s s th e iso l a t i o n ba rri e r . f i gur e 48 sh o w s a typ i ca l ga lvan ica l ly-is o l a t e d c o nf igura t io n usin g t h e ad50 61. the p o wer su p p ly t o t h e p a r t als o n e e d s t o be is ola t e d ; t h is is acco m p lish e d b y usin g a tra n sf o r m e r . on t h e d a c side o f t h e t r a n sfo r m e r , a 5 v r e gu la t o r p r o v i d es t h e 5 v s u p p l y r e q u ir ed f o r th e ad5061 . 0. 1 f 10 f v dd gn d po w e r 5v re g u l a to r a d 5061 04 76 2- 03 8 adu m1 3 0 x sc l k v0 a v1 a sc l k v ou t sy n c v0 b v1 b sd i di n v0 c v1 c da t a fig u re 4 8 . a d 50 6 1 wit h a ga lv an ic a lly -is o lat e d int e rf ac e power supply bypass ing and gr ounding w h en acc u rac y is im p o r t an t in a cir c ui t, i t is hel p f u l t o ca r e f u l l y c o ns i d e r t h e p o we r supply an d g rou nd re tu r n l a y o ut on t h e bo a r d . the p r in t e d cir c u i t bo a r d co n t ainin g t h e ad5061 sh o u l d ha v e s e pa ra t e an alog a n d digi ta l sectio n s , e a c h ha vin g i t s o w n a r e a o f t h e b o a r d . i f t h e ad506 1 is in a sys t em w h er e o t h e r de vices r e q u ir e a n a g nd-t o - d g nd co nn e c tion, t h en t h e c o n n e c t i on s h o u l d b e m a d e a t one p o i n t on ly . t h i s g rou n d p o in t sh o u ld be as c l os e as p o s s ib le t o t h e ad50 61. the p o wer s u p p l y t o th e ad506 1 s h o u l d b e b y p a s s ed wi t h 10 f a n d 0.1 f ca p a ci t o rs. the ca p a c i t o rs sh ou ld be ph ysical ly as c l os e as p o s s ib le t o t h e de vic e wi th t h e 0.1 f ca p a ci t o r ide a l l y r i g h t u p a g a i ns t t h e de vi ce . th e 10 f c a p a ci t o rs a r e t h e ta n t al um be a d type . i t i s im po r t a n t tha t t h e 0. 1 f ca pa ci t o r h a s lo w ef fe c t i v e s e r i es r e sis t a n c e (es r ) a n d ef fe c t i v e s e r i es ind u c t an c e (es i ), as do co mm on cera mic typ e s o f ca p a ci t o rs. this 0.1 f ca p a ci t o r p r o v ides a lo w im p e dan c e p a th t o g r o u nd fo r hig h f r e q uen c ies ca us e d b y t r a n sien t c u r r en ts d u e t o in t e r n al log i c swi t ching. the p o wer s u p p l y lin e i t s e lf sh ou ld ha v e as la rg e a trace as p o s s i b le t o p r o v ide a lo w im p e da n c e p a th and red u ce g l i t ch ef fe c t s o n t h e s u p p ly lin e . c l o c ks a n d o t h e r fas t swi t chi n g d i g i t a l s i g n a l s s h ou l d b e sh i e l d e d f rom ot he r p a r t s of t h e b o ard b y d i g i t a l g rou n d . a v oi d c r o s s o ve r of d i g i t a l a n d an a l o g s i g n a l s , if p o s s i b l e . w h en traces cr os s o n o p p o si te sides o f th e bo a r d , en s u r e tha t t h ey r u n a t r i g h t a n g l es t o eac h o t her t o r e d u ce f e e d t h rou g h e f f e c t s t h rou g h t h e b o ard. t h e b e st b o ard l a y o ut t e chni q u e is t h e micr os t r i p t e chniq u e w h er e t h e co m p on en t side o f t h e b o a r d is de dic a te d to t h e g r o u n d pl a n e on ly , an d t h e sig n al traces a r e p l aced on t h e s o lder side . h o wev e r , this is n o t a l wa ys p o ss i b le wi t h a 2- la yer b o a r d .
ad5061 rev. a | page 20 of 20 outline dimensions 13 5 6 2 8 4 7 2. 90 bs c 1. 60 bs c 1.95 bsc 0. 65 bs c 0. 38 0. 22 0. 15 m a x 1. 3 0 1. 1 5 0. 9 0 seating plane 1 . 45 m a x 0. 2 2 0. 0 8 0. 6 0 0. 4 5 0. 3 0 8 4 0 2. 80 bs c pin 1 indicator compliant to jedec standards mo-178-ba fig u re 4 9 . 8-le ad s m a l l out l ine tr ans i s t or p a ck ag e [sot- 23] (rj-8) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model t e mper a t ur e r a n g e i n l d e s c r i p t i o n p a ck age description p a ck age op t i o n b r a n d i n g ad5061brjz - 1reel7 1 ?40c to +85c 4 lsb 2.7 v to 5.5 v , r e set to 0 v 8-l e ad so t - 23 rj-8 d43 ad5061brjz - 1500rl7 1 ?40c to +85c 4 lsb 2.7 v to 5.5 v , r e set to 0 v 8-l e ad so t - 23 rj-8 d43 ad5061brjz - 2reel7 1 ?40c to +85c 4 lsb 2 . 7 v t o 5 . 5 v , r e s e t t o m i d s c a l e 8-l e ad so t - 23 rj-8 d44 ad5061brjz - 2500rl7 1 ?40c to +85c 4 lsb 2 . 7 v t o 5 . 5 v , r e s e t t o m i d s c a l e 8-l e ad so t - 23 rj-8 d44 ad5061y rjz - 1500rl7 1 ?40c to +125c 4 lsb 2.7 v to 5.5 v , r e set to 0 v 8-l e ad so t - 23 rj-8 d6g ad5061y rjz - 1r eel7 1 ?40c to +125c 4 lsb 2.7 v to 5.5 v , r e set to 0 v 8-l e ad so t - 23 rj-8 d6g e v al - a d5061eb e v alua t i o n boar d 1 z = pb-free part. ?2006 analo g devi ces, inc. all rights reserve d . tra d em ar ks and registered tra d emar ks are the prop erty of their respective o w ners . d04762-0-1/06(a)

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